1. Technical Field
This invention relates generally to the field of semiconductors, and more particularly, to manufacturing approaches used in forming diffusion breaks during processing of integrated circuits and other devices.
2. Related Art
A typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., field effect transistors (FETs)) and connect the devices into circuits. In a typical state of the art complementary insulated gate FET process, such as what is normally referred to as CMOS, layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer. A simple FET is formed by the intersection of two shapes, a gate layer rectangle on a silicon island formed from the silicon surface layer. Each of these layers of shapes, also known as mask levels or layers, may be created or printed optically through well known photolithographic masking, developing and level definition, e.g., etching, implanting, deposition and etc.
Mask shapes each may be grouped into one of four types: line/space arrays, isolated lines, isolated spaces, and contact holes. Ideally, fabrication parameters such as process biases applied to features on a particular layer affects all types of features uniformly on that layer. Unfortunately, all feature types do not respond uniformly. In particular, isolated lines and minimum pitch line/space arrays known as contact pitch lines behave differently to focus. Contacted pitch lines are minimum pitch line/space arrays on a particular layer in the minimum line width and spacing plus additions for via or contact covers or landing pads. When printed out-of-focus, contact pitch lines get wider (and spaces shrink), while isolated lines get narrower. This dichotomy has become especially troublesome, as image dimensions have shrunk.
As shown in FIG. 1, an exemplary current art device 10 has a diffusion break 12 formed beneath the dummy gate 14 of device 10 prior to source/drain formation. However, at the 20 nm technology node and beyond, this approach suffers from one or more of the following deficiencies: a) poor source/drain growth at active region (Rx) and Fin edge, b) contact (CA) punch-through at Rx and Fin ends, and c) device variability. Furthermore, existing solutions either increase standard cell width by at least 1 contacted poly pitch (CPP), or are not capable of ensuring adequate coverage for Rx and Fin tuck, thus costing device yield and performance. Therefore, what is needed is an approach that solves one or more deficiencies of the current art.